Senior Physical Design Engineer (CDNS Flow)

As a Senior Physical Design Engineer (Back-End Digital IC Design Engineer), you will be a key contributor to our startup’s success. Your role will involve designing and implementing cutting-edge digital integrated circuits (ICs) using Cadence EDA tools. If you’re passionate about pushing the boundaries of technology, thriving in a dynamic environment, and wanting to make a significant impact, Hyphen Deux encourages you to apply!

Senior Physical Design Engineer

Responsibilities of Senior Physical Design Engineer:

  • Design and Implementation: review purchased IP data, deliverable schedule, tool flows, licenses, and PDK with cross-function teams
  • Floor planning and Place-and-Route: Utilize Cadence Digital Implementation tools for floor planning, placement, CTS, and routing. Optimize power, performance, and area (PPA) metrics.
  • Clock Tree Synthesis (CTS): Create efficient clock distribution networks to meet timing requirements.
  • Static Timing Analysis (STA): Perform STA to ensure timing closure and meet design specifications.
  • Physical Verification: Work on DRC (Design Rule Check) and LVS (Layout vs. Schematic) checks to ensure design manufacturability.
  • Collaboration: Collaborate with cross-functional teams, including front-end designers, verification engineers, and packaging experts, to ensure seamless integration.
  • Low-Power Design: Implement low-power techniques such as clock gating, power gating, and voltage scaling as a plus.



  • Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
  • Experience:
  • 7 years of Experience for BA/BSc. or > 5 years of Experience for MSc Physical Design for digital block-level or mixed-signal development. Top-level Experience is a plus.
  • Strong Experience with Cadence PnR tools and in digital IC design using Tempus, LEC, Quantus, Voltus, and PVS.
  • Familiarity with the complete back-end design flow, including EDA flow setup with EDA AE, place-and-route, synthesis, and sign-off.



  • Knowledge of Foreplaning, CTS, Power, and static timing analysis.
  • Understanding of low-power design methodologies.
  • Scripting skills (Linux, Shell, Tcl, jobs scheduling) for automation.
  • Excellent teamwork, communication, and analytical skills
  • Able to learn quickly and results-oriented
  • Proficiency in Verilog, UPF, and full digital design flow is a plus.
  • Good communication, presentation, and documentation skills in English
  • Problem-solving: Ability to address design challenges and have ambitions to resolve new tool and flow issues.
  • Team Player: Thrive in a collaborative startup environment with excellent support from the team, EDA, and IP vendors.



o Working with world-leading IP providers and their expert teams

o Professional, innovative, and joyful working environment

o Great opportunity for improving knowledge and Experience with lots of technical training materials and expert teams

o Competitive Salary and Benefit

o Insurance plan based on full salary + 13th salary + performance bonus

o Working in a fast-paced, flexible, and multinational working environment

o Make a new chapter for the Vietnam semiconductor industry.



Our startup is based in SHTP, Ho Chi Minh City, Vietnam. We offer flexible work arrangements if necessary, including remote options.

How to apply

If you’re excited about shaping the future of digital ICs in Vietnam and have expertise in Cadence EDA flow, please submit your resume and a cover letter to email:

Join us in revolutionizing the semiconductor industry!

Apply for this position

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